This invention relates to liquid crystal display (LCD) panels and more particularly to testing of LCD panels.
LCD panels are widely used as flat panel display devices. As is well known to those having skill in the art, an LCD panel includes a pixel region, also known as an active region, which includes an array of pixel thin film transistors and intersecting arrays of spaced apart data lines and gate lines that are connected to the array of pixel thin film transistors. The array of pixel thin film transistors, data lines and gate lines form an array of addressable pixels.
In fabricating LCD panels, a gross test is generally carried out in order to check the operation of the pixels of an LCD panel prior to mounting driver integrated circuit chips to the LCD panel. Thus, defective LCD panels can be identified prior to mounting driver chips to the panel. In order to perform a gross test of the pixels, all of the gate lines and data lines generally are energized so that defective pixels can be readily identified by visual inspection of the panel.
LCD panels may be classified in two general types, depending upon the configuration of driver chips that are mounted on the LCD panel. In one panel type, tape automated bonding (TAB) is used to mount driver chips on the LCD panel. In a second panel type, chip on glass (COG) technology is used to mount driver chips on the LCD panel. Depending on the type of LCD panel, gross testing may be performed differently.
Each of the types of LCD panels, and conventional gross testing thereof will now be described. In general, pin contact testing is applied to TAB LCD panels and conductive rubber pad testing is generally applied to COG technology.
FIG. 1 illustrates a conventional LCD panel using TAB mounting technology. In TAB mounting technology, the LCD panel is connected to the TAB driver chips using a conductive film. The TAB driver chips are generally connected to a printed circuit board. Referring now to FIG. 1, an LCD panel 10 includes a substrate 11 such as a glass substrate including a pixel region 13. As already described, the pixel region 13 includes therein an array of pixel thin film transistors and intersecting arrays of spaced apart data lines and gate lines connected to the array of pixel thin film transistors. In the LCD panel of FIG. 1, the gate lines extend horizontally and the data lines extend vertically. A color filter substrate may be included on the glass substrate 11. The color filter substrate may include color filter patterns.
Still referring to FIG. 1, the gate lines 15 extend outside the pixel region 13 to a gate line area 17 on substrate 11. As shown, the gate lines may extend outside the pixel region at opposite sides thereof. Similarly, the data lines 19 extend outside the pixel regions 13 into a data line area 21. The data lines 19 may also extend beyond the pixel region at the opposite side thereof.
In order to perform a gross test on the LCD panel 10, respective ends of the gate lines 15 are connected to a gate contact line 23 in the gate line area 17. Similarly, the respective ends of the data lines 19 are connected to a data contact line 25 in the data line area 21. Voltage is supplied to the gate lines 15 and the data lines 19 through the gate contact line 23 and the data contact line 25 during the gross test. A gate pin contact pad 24 and a data pin contact pad 26 are respectively formed at the ends of the gate contact line 23 and the data contact line 25. Probes from a test fixture contact the respective contact pads 24 and 26 during testing.
In order to test the LCD panel 10, power is supplied to the gate contact line 23 and the data contact line 25 by contacting probes from a test fixture to the gate pin contact pad 24 and the data pin contact pad 26. When power is applied to the gate pin contact pad 24 and the data pin contact pad 26, current flows through all of the gate lines 15 and all of the data lines 19. This causes all of the pixel thin film transistors in the array to be energized to thereby activate all of the pixels. For example, for an LCD panel that is normally white, all of the pixels will change to black. Conversely, for an LCD panel that is normally black, all of the pixels will change to white. If there is a defect in the data lines, gate lines or any of the pixel thin film transistors in the array, one or more of the pixels will remain in its original state. It is therefore possible to visually discriminate good LCD panels from defective LCD panels by monitoring the displayed state of the pixels.
After completion of the gross test, it is generally desirable to be able to address each of the data lines and gate lines individually for normal operation. Accordingly, the gate contact line 23 and the data contact line 25 are removed from the substrate 11 prior to attaching the driver chips in the gate area 17 and the data area 21. Glass cutting may be used to cut the substrate 11 along dashed lines 27 to remove the portion of the substrate including the gate contact line 23, gate pin contact pad 24, data contact line 25 and data pin contact pad 26. Alternatively, laser cutting may be used to cut the data lines 19 and the gate lines 15 in the data line area 21 and the gate line area 17 respectively, to thereby electrically disconnect the data contact line 25 and the gate contact line 23 from the data lines 19 and gate lines 15, respectively.
Unfortunately, each of these cutting operations may adversely impact the LCD panel. More specifically, when using the glass cutting, glass particles may contaminate the LCD panel. Laser cutting may be slower and more expensive so that increased cost may result. Moreover, both of these operations use additional mechanical steps to physically disconnect the gate contact line 23 and the data contact line 25 from the gate lines 15 and the data lines 19, respectively. These additional operations can result in decreased yields for the LCD panels, and in increased costs.
Gross testing of COG LCD panels will now be described. As shown in FIG. 2A, a conventional COG LCD panel 30 includes a substrate 31 and a pixel region 33 as already described. A color filter substrate may also be attached to the glass substrate 31. A gate line area 35 is provided outside the pixel region 33 and a data line area 37 is provided outside the pixel region 33. In gate line area 35, a plurality of gate lines 39 end in multi-sided subgroups of gate lines. In FIG. 2A, two multi-sided subgroups of gate lines are shown however it will be recognized that more subgroups may be provided. One or more gate driver chips may be attached to a multi-sided gate line subgroup.
Similarly, in the data line area 37 a plurality of data lines 41 end in a plurality of multi-sided data line subgroups. Four multi-sided subgroups are shown in data line area 37, but fewer or more subgroups can be used. Driver chips are attached to the data lines in the multi-sided subgroups. As also shown in FIGS. 2A-2B, bonding pads 43 are generally formed at the ends of the data lines 41 and gate lines 39 to facilitate bonding of the chips to the bonding pads 43.
A test apparatus or fixture for performing gross tests on the LCD panel 30 of FIG. 2A generally uses spaced apart conductive rubber pads to simultaneously energize the bonding pads 43. A schematic prospective view of a gross test fixture for testing the LCD panel of FIG. 2A is shown in FIG. 3.
As shown in FIG. 3, the test fixture 50 includes a base 51 having a recessed portion 58. Printed circuit boards 53 project from the bottom of the recessed portion 58 of the base 51 to support and test the LCD panel 30. Guide projections 55 are formed along the edges of the printed circuit boards 53, to hold the LCD panel 30 in place between the printed circuit boards 53.
Still referring to FIG. 3, conductive rubber pads 57 are attached to the tops of the printed circuit boards 53. The conductive rubber pads 57 are arranged in spaced apart relation corresponding to the multi-sided subgroups 39 of gate lines 39 and data lines 41 in the gate line area 35 and the data line area 37, respectively. A power source 59 is connected to the printed circuit boards 53 so that the conductive rubber pads 57 can be supplied with power.
A hinged cover 63 covers the base 51 during the gross tests. A projection 65 is formed on the bottom of the cover 63. The projection 65 contacts the substrate 31 and presses the conductive rubber pads 57 into contact with the multi-sided subgroups of gate lines and data lines when the cover is closed.
Accordingly, in order to provide a gross test of a COG LCD panel, the LCD panel 30 is loaded onto the printed circuit boards 53. The gate lines 39 and the data lines 41 of the LCD panel 30 contact the conductive rubber pads 57 on the tops of the printed circuit boards 53. The hinged cover 63 is closed. The projection 65 presses the LCD panel 30 so that the gate lines 39 and data lines 41 are tightly coupled to the conductive rubber pads 57.
When voltage is supplied to the conductive rubber pads 57, conductive particles in the conductive rubber pads are supplied with the voltage. As a result, all of the gate lines 39 and data lines 41 in contact with the conductive particles are also energized. This causes the pixels of the LCD panel to change from their unenergized state, for example white, to their energized state, for example black. If any of the data lines, gate lines or pixel thin film transistors are defective, the corresponding pixels will not be energized and will not change color. An operator can thereby determine the quality of the LCD panel by visual inspection.
Unfortunately, the gross test of LCD panels using the conductive rubber pads may be prone to errors. In particular, if any of the gate lines 39 or data lines 41 does not electrically contact a conductive particle in the conductive rubber pad 57, the LCD panel may appear to be defective upon visual inspection, even though it is not in fact defective. A high resolution LCD panel has large numbers of gate lines 39 and data lines 49, and the distance between the lines can be very small. The distance between the conductive particles in the conductive rubber pads may be larger than the distance between adjacent gate lines or data lines. Moreover, the number of conductive particles may be limited. Accordingly, it is possible that a data line or a gate line does not contact a conductive particle.
If a data line or gate line is between the conductive particles, the line will not be energized and the associated pixels will not change color. Accordingly, on visual inspection, the LCD panel will appear defective even though it is not defective.
It is therefore an object of the present invention to provide improved LCD panels and methods of gross testing thereof.
It is another object of the present invention to provide improved LCD panels which do not require physical disconnection of elements in the gate line area or data line area after gross testing.
It is yet another object of the present invention to provide LCD panels and gross testing methods therefor which do not require the use of conductive rubber pads for gross testing.
It is still another object of the present invention to provide LCD panels and gross testing methods therefor which can reduce the possibility of a good LCD panel from appearing defective in a gross test.
These and other objects are provided according to the present invention by providing a plurality of test thin film transistors outside the pixel region of an LCD panel that includes an array of pixel thin film transistors and intersecting arrays of spaced apart data lines and gate lines connected to the array of pixel thin film transistors. A respective test thin film transistor is connected to a respective one of the data lines or gate lines. At least subgroups of the test thin film transistors are commonly connected to provide common energization of subgroups of data lines or gate lines for gross testing of the LCD panels.
By providing test thin film transistors outside the pixel region, and commonly connecting at least subgroups of data lines or test lines, the commonly connected subgroups can be energized for gross testing of the LCD panel. Rubber pads are not required to energize each individual data line or gate line because the commonly connected subgroups of test thin film transistors can be energized as a unit. Moreover, after testing is completed, the test thin film transistors need not be disconnected. Rather, they simply need not be energized after the gross test. The unenergized test thin film transistors act as a high impedance that isolates the data lines and test lines from one another as if they were not interconnected by the test transistors. Accordingly, efficient testing of LCD panels may be provided, without the need to physically cut lines after testing and without the possibility of introducing errors by high density conductive rubber pad contacts to each of the data lines and gate lines.
In one embodiment of the present invention, which is particularly suitable for tape automated bonding (TAB) LCD panels, all the test thin film transistors that are connected to data lines are commonly connected to provide common energization of all data lines, and all the test thin film transistors that are connected to gate lines are commonly connected to provide common energization of all gate lines. In another embodiment which may be particularly suitable for chip on glass (COG) LCD panels, subgroups of the test thin film transistors that are connected to subgroups of data lines are commonly connected to provide common energization of subgroups of data lines and subgroups of the test thin film transistors that are connected to subgroups of gate lines are commonly connected to provide common energization of subgroups of gate lines.
LCD panels as described above may be used with a test fixture that energizes all the test thin film transistors that are commonly connected to data lines and energizes all the test thin film transistors that are commonly connected to gate lines. Alternatively, the test fixture energizes all the subgroups of test thin film transistors that are commonly connected to gate lines.
More specifically, according to the present invention, LCD panels comprise a pixel region and a plurality of test thin film transistors outside the pixel region. The pixel region includes an array of pixel thin film transistors and intersecting arrays of spaced apart data lines and gate lines connected to the array of pixel thin film transistors. Each test thin film transistor includes a source, a drain and a gate. One of the source and drain of a respective test thin film transistor is connected to a respective one of the data lines or gate lines. The other of the sources and drains of the test thin film transistors are commonly connected. The gates of the test thin film transistors are commonly connected.
In a specific embodiment, the drain of a respective test thin film transistor is connected to a respective one of the gate lines, the sources of the test thin film transistors are commonly connected and the gates of the test thin film transistors are commonly connected. Respective drains of the remaining test thin film transistors are connected to a respective one of the data lines. The sources of the remaining test thin film transistors are commonly connected and the gates of the test thin film transistors are commonly connected. This configuration is particularly useful for testing of TAB LCD panels.
In another embodiment, the drain of a respective test thin film transistors is connected to a respective one of the gate lines, the sources of subgroups of the test thin film transistors are commonly connected to provide a plurality of common source connections and the gates of subgroups of the test thin film transistors are commonly connected to provide a plurality of common gate connections. The drains of others of the respective test thin film transistors are connected to a respective one of the data lines. The sources of the subgroups of the test thin film transistors are commonly connected to provide a plurality of common source connections and the gates of the subgroups of the test thin film transistors are commonly connected to provide a plurality of common gate connections.
Even more specifically, in one embodiment each of the gate lines includes first and second ends and the drain of a respective test thin film transistor is connected to the first end of a respective one of the gate lines. Each of the data lines includes first and second ends and the drain of a respective test thin film transistor is connected to the first end of a respective one of the data lines. Each of the gate lines can include a bonding pad at the first end thereof, and the drain of a respective test thin film transistor is connected to the bonding pad of the first end of a respective one of the gate lines. Similarly, each of the data lines can include a bonding pad at the first end thereof, and the drain of a respective test thin film transistor is connected to the bonding pad of the first end of a respective one of the data lines.
The bonding pads may be arranged in a row at the first ends for tape automated bonding of gate driver chips thereto or may be arranged in multi-sided groups at the first ends of the gate lines for chip on glass mounting of gate driver chips thereto. Similar arrangements may be provided for the data lines for tape automated bonding of data driver chips or for chips on glass mounting of data driver chips thereto. In yet another alternative, each of the gate lines and data lines includes a bonding pad at the first end thereof, and the drain of a test of a respective test thin film transistor is connected to the second end of a respective one of the gate lines or data lines.
In the TAB embodiments described above, the sources of the test thin film transistors that are connected to the gate lines can be commonly connected to a first gate probe contact and the gates of these test thin film transistors can be commonly connected to a second gate probe contact. Similar connections may be provided for the test thin film transistors connected to the data lines using a first data probe contact and a second data probe contact. In the COG LCD panels, a plurality of first gate probe contacts and a plurality of second gate probe contacts may be provided wherein the sources of subgroups of the test thin film transistors are commonly connected to a respective one of the first gate probe contacts to provide a plurality of common source connections and the gates of subgroups of the test thin film transistors are commonly connected to a respective one of the second gate probe contacts to provide a plurality of common gate connections. A plurality of first and second data probe contacts may also be provided.
LCD panels as described above may be gross tested by contacting the LCD panels by a test fixture. The test fixture energizes the first and second gate probe contacts and the first and second data probe contacts in the TAB embodiment. The test fixture energizes the plurality of first and second gate probe contacts and the plurality of first and second data probe contacts in the COG embodiment. High density conductive rubber pads are not required and physical disconnection of test structures need not be provided after gross testing.
Methods are also provided, according to the present invention, for gross testing an LCD panel comprising a pixel region including an array of pixel thin film transistors and intersecting arrays of spaced apart data lines and gate lines connected to the array of pixel thin film transistors. The LCD panel is tested by fabricating a plurality of test thin film transistors outside the pixel region, a respective one of which is connected to a respective one of the data lines or gate lines, wherein at least subgroups of the test thin film transistors are commonly connected. The subgroups of the test thin film transistors that are commonly connected are then energized.
In one embodiment, all the test thin film transistors that are connected to data lines are commonly connected and all the test thin film transistors that are connected to gate lines are commonly connected. In this embodiment, the energizing step comprises the step of energizing the commonly connected test thin film transistors that are connected to all data lines and energizing the commonly connected test thin film transistors that are connected to all gate lines. This embodiment may be used to test TAB LCD panels.
In another embodiment, subgroups of the test thin film transistors that are connected to data lines are commonly connected and subgroups of the test thin film transistors that are connected to gate lines are commonly connected. In this embodiment, the energizing step comprises the step of energizing the subgroups of commonly connected test thin film transistors that are connected to data lines and energizing the subgroups of commonly connected test thin film transistors that are connected to gate lines. This embodiment may be used with COG LCD panels.
The energizing step is preferably performed by a test fixture. In the TAB embodiment, at least first and second test probes are included at locations corresponding to the commonly connected test thin film transistors that are connected to all data lines and the commonly connected test thin film transistors that are connected to all gate lines. In the COG embodiment a least first and second groups of probes are included in the test figure fixture at locations corresponding to the subgroups of commonly connected test thin film transistors that are connected to data lines and the subgroups of commonly connected test thin film transistors that are connected to gate lines.
In fabricating the LCD panels, the array of pixel thin film transistors and plurality of test thin film transistors are preferably fabricated simultaneously using common fabrication steps. The source, drain and gate connections of the test thin film transistors may be provided as was already described. Accordingly, high speed, reliable gross testing of LCD panels may be provided.